Although much has been achieved by CMOS scaling and progress continues with 3D chip stacking, this approach isn�t necessarily the optimal solution to every problem. Heterogeneous integration of disparate materials, thermal management, chip design, and Known-Good-Die issues are some of the obstacles that industry is still working to overcome. Quilt Packaging� (QP), offered by Indiana Integrated Circuits (IIC) and RTI International, offers a new choice for dense, low-power, and cost-effective systems-in-package. With customizable interconnect geometries, submicron alignment, ultra-wide bandwidth/ultra-low loss (< 0.1 dB insertion loss 50 MHz through 100 GHz), Quilt Packaging is a platform technology which is rapidly maturing in the aerospace/defense market. IIC has licensed QP technology for large format arrays, enabling customers to partition large, poorly-yielding integrated circuits into smaller, higher-yielding chips which are then tiled into arbitrarily large arrays. This is made possible by QP�s ability to deliver chip-to-chip gap (<10 um) while maintaining sub-micron alignment. Revolutionary system improvements are also underway for microwave/RF, power, and optical applications. 2013 saw a major increase in activity and industry interest in the technology, with application to a variety of high performance defense systems. As the technology matures, we anticipate a crossover to commercial applications, particularly in power. IIC believes the adoption of Quilt Packaging will continue to increase with the number of successfully deployed Quilt-Packaged systems on the rise in 2014. Demonstrations are currently underway in a variety of material systems, including GaAs, GaSb, InP, SiC and GaN. We look forward to working closely with our customers to provide game-changing system performance increases while decreasing costs and SWAP through Quilt Packaging this year.